View MT29F2G08AACWP_41725.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

2Gb, 4GB, 8Gb: x8, x16 NAND Flash Memory Features
NAND Flash Memory
MT29F2G08AACWP, MT29F4G08BACWP, MT29F8G08FACWP
For the latest data sheet, please refer to the Micron Web site: www.micron.com/datasheets
Features
* Organization * Page size x8: 2,112 bytes (2,048 + 64 bytes) * Page size x16: 1,056 words (1,024 + 32 words) * Block size: 64 pages (128K + 4K bytes) * Device size: 2Gb: 2,048 blocks; 4Gb: 4,096 blocks; 8Gb: 8,192 blocks * READ performance * RANDOM READ: 25s * SEQUENTIAL READ: 30ns (3V x8 only) * WRITE performance * PROGRAM PAGE: 300s (TYP) * BLOCK ERASE: 2ms (TYP) * Endurance: 100,000 PROGRAM/ERASE cycles * First block (block address 00h) guaranteed to be valid without ECC (up to 1,000 PROGRAM/ERASE cycles) * VCC: 1.70V-1.95V1 or 2.7V-3.6V * Automated PROGRAM and ERASE * Basic NAND Flash command set: * PAGE READ, READ for INTERNAL DATA MOVE, RANDOM DATA READ, READ ID, READ STATUS, PROGRAM PAGE, RANDOM DATA INPUT, PROGRAM PAGE CACHE MODE, PROGRAM for INTERNAL DATA MOVE, BLOCK ERASE, RESET * New commands: * PAGE READ CACHE MODE * One-time programmable (OTP), including: OTP DATA PROGRAM, OTP DATA PROTECT, OTP DATA READ * READ UNIQUE ID (contact factory) * READ ID2 (contact factory) * Operation status byte provides a software method of detecting: * PROGRAM/ERASE operation completion * PROGRAM/ERASE pass/fail condition * Write-protect status * READY/BUSY (R/B#) pin provides a hardware method of detecting PROGRAM or ERASE cycle completion * PRE pin: prefetch on power up (3V device only)2 * WP# pin: hardware write protect
www..net
Figure 1:
48-Pin TSOP Type 1
Options
* Density: 2Gb (single die) 4Gb (dual-die stack) 8Gb (quad-die stack) * Device width: x8 x161 * Configuration: # of die # of CE# # of R/B# 1 1 1 2 1 1 4 2 2 * VCC: 2.7V-3.6V 1.70V-1.95V1 * Third generation die * Package: 48-Pin TSOP type I (lead-free) * Operating temperature: Commercial (0C to 70C) Extended (-40C to +85C)3
Marking
MT29F2G MT29F4G MT29F8G MT29Fxx08x MT29Fxx16x
A B F A B C WP None ET
Notes: 1. Packaged parts are only available for 3V x8 devices. For 1.8V or x16 devices, contact factory. 2. The PRE function is not supported on ET and 1.8V devices. Contact factory. 3. For ET devices, contact factory. 1
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved.
PDF: 09005aef814b01a2 / Source: 09005aef814b01c7 2_4_8gb_nand_m49a__1.fm - Rev. A 3/06 EN
Products and specifications discussed herein are subject to change by Micron without notice.
2Gb, 4GB, 8Gb: x8, x16 NAND Flash Memory Part Numbering Information
Part Numbering Information
Micron(R) NAND Flash devices are available in several different configurations and densities (see Figure 2). Figure 2: Part Number Chart
MT 29F 2G 08 Micron Technology Product Family
29F = Single-supply NAND Flash memory
A
A
C
WP
ES
:C Die Revision
C = First generation
Production Status
Blank = Production ES = Engineering sample MS = Mechanical sample QS = Qualification sample
Density
2G = 2Gb 4G = 4Gb 8G = 8Gb
Operating Temperature Range
Blank = Commercial (0C to +70C) ET = Extended (-40C to +85C)
Device Width
08 = 8 bits 16 = 16 bits
Reserved for Future Use Feature Set
I/O
Classification
# of die # of CE# # of R/B#
Blank = Standard features
A B F
1 2 4
1 1 1
1 1 1
Common Common Common
Package Codes
WP = 48-pin TSOP I (lead-free)
Generation Operating Voltage Range
A = 3.3V (2.70V-3.60V) B = 1.8V (1.70V-1.95V) A = First-generation die B = Second-generation die C = Third-generation die
Valid Part Number Combinations
www..net
After building the part number from the part numbering chart above, verify that the part number is valid using the Micron Parametric Part Search at: http://www.micron.com/ partsearch. If the device required is not on this list, contact the factory.
PDF: 09005aef814b01a2 / Source: 09005aef814b01c7 2_4_8gb_nand_m49a__1.fm - Rev. A 3/06 EN
2
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved.
2Gb, 4GB, 8Gb: x8, x16 NAND Flash Memory Table of Contents Table of Contents
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Part Numbering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 Valid Part Number Combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Memory Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Bus Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Address Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Data Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 READs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Ready/Busy# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Power-On AUTO-READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Command Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 READ Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 PAGE READ 00h-30h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 RANDOM DATA READ 05h-E0h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 PAGE READ CACHE MODE Start 31h; PAGE READ CACHE MODE Start Last 3Fh . . . . . . . . . . . . . . . . .24 READ ID 90h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 READ STATUS 70h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 PROGRAM Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 PROGRAM PAGE 80h-10h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 SERIAL DATA INPUT 80h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 RANDOM DATA INPUT 85h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 PROGRAM PAGE CACHE MODE 80h-15h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Internal Data Move . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 READ FOR INTERNAL DATA MOVE 00h-35h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 PROGRAM for INTERNAL DATA MOVE 85h-10h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 BLOCK ERASE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 BLOCK ERASE 60h-D0h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 One Time Programmable (OTP) Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 OTP DATA PROGRAM A0h-10h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 OTP DATA PROTECT A5h-10h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 OTP DATA READ AFh-30h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 RESET Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 RESET FFh. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 WRITE PROTECT Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 Error Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 VCC Power Cycling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 Timing Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
www..net
PDF: 09005aef814b01a2 / Source: 09005aef814b01c7 2_4_8gb_nand_m49aTOC.fm - Rev. A 3/06 EN
3
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved.
2Gb, 4GB, 8Gb: x8, x16 NAND Flash Memory List of Figures List of Figures
Figure 1: Figure 2: Figure 3: Figure 4: Figure 5: Figure 6: Figure 7: Figure 8: Figure 9: Figure 10: Figure 11: Figure 12: Figure 13: Figure 14: Figure 15: Figure 16: Figure 17: Figure 18: Figure 19: Figure 20: Figure 21: Figure 22: Figure 23: Figure 24: Figure 25: Figure 26: Figure 27: Figure 28: Figure 29: Figure 30: Figure 31: Figure 32: Figure 33: Figure 34: Figure 35: Figure 36: Figure 37: Figure 38: Figure 39: Figure 40: Figure 41: Figure 42: Figure 43: Figure 44: Figure 45: Figure 46: Figure 47: Figure 48: Figure 49: Figure 50: Figure 51: Figure 52: Figure 53: Figure 54: Figure 55: Figure 56:
www..net
48-Pin TSOP Type 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Part Number Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 NAND Flash Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 48-Pin TSOP Type 1 Pin Assignments (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Memory Map x8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Memory Map x16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Array Organization for MT29F2G08AxC (x8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Array Organization for MT29F2G16AxC (x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Array Organization for MT29F4G08BxC and MT29F8G08FxC (x8) . . . . . . . . . . . . . . . . . . . . . . . .15 Array Organization for MT28F4G16BxC and MT29F8G16FxC (x16) . . . . . . . . . . . . . . . . . . . . . . .16 Time Constants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Minimum Rp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 READY/BUSY# Open Drain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 tFall and tRise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Iol vs. Rp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 First Page Power-On AUTO-READ (3V devices only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 PAGE READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 RANDOM DATA READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 PAGE READ CACHE MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 READ ID Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Status Register Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 PROGRAM and READ STATUS Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 RANDOM DATA INPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 PROGRAM PAGE CACHE MODE Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 INTERNAL DATA MOVE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 INTERNAL DATA MOVE with RANDOM DATA INPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 BLOCK ERASE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 OTP DATA PROGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 OTP DATA PROTECT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 OTP DATA READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 RESET Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 ERASE Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 ERASE Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 PROGRAM Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 PROGRAM Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 AC Waveforms During Power Transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 COMMAND LATCH Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 ADDRESS LATCH Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 INPUT DATA LATCH Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 SERIAL ACCESS Cycle After READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 READ STATUS Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 PAGE READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 PAGE READ Operation with CE# "Don't Care" . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 RANDOM DATA READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 PAGE READ CACHE MODE Timing Diagram, Part 1 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 PAGE READ CACHE MODE Timing Diagram, Part 2 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 PAGE READ CACHE MODE Timing without R/B#, Part 1 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . .52 PAGE READ CACHE MODE Timing without R/B#, Part 2 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . .53 READ ID Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 PROGRAM PAGE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 PROGRAM PAGE Operation with CE# "Don't Care" . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 PROGRAM PAGE Operation with RANDOM DATA INPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 INTERNAL DATA MOVE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 PROGRAM PAGE CACHE MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 PROGRAM PAGE CACHE MODE Ending on 15h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 BLOCK ERASE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 4
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved.
PDF: 09005aef814b01a2 / Source: 09005aef814b01c7 2_4_8gb_nand_m49aLOF.fm - Rev. A 3/06 EN
2Gb, 4GB, 8Gb: x8, x16 NAND Flash Memory List of Figures
Figure 57: Figure 58: RESET Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 TSOP Type I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
www..net
PDF: 09005aef814b01a2 / Source: 09005aef814b01c7 2_4_8gb_nand_m49aLOF.fm - Rev. A 3/06 EN
5
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved.
2Gb, 4GB, 8Gb: x8, x16 NAND Flash Memory List of Tables List of Tables
Table 1: Table 2: Table 3: Table 4: Table 5: Table 6: Table 7: Table 8: Table 9: Table 10: Table 11: Table 12: Table 13: Table 14: Table 15: Table 16: Table 17: Table 18: Table 19: Table 20: Table 21: Table 22: Pin/Pad Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Operational Example (x8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Operational Example (x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Array Addressing: MT29F2G08AxC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Array Addressing: MT29F2G16AxC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Array Addressing for MT29F4G08BxC and MT29F8G08FxC (x8) . . . . . . . . . . . . . . . . . . . . . . . . . .15 Array Addressing for MT28F4G16BxC and MT29F8G16FxC (x16) . . . . . . . . . . . . . . . . . . . . . . . . .16 Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Command Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Device ID and Configuration Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Status Register Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Status Register Contents After RESET Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 Absolute Maximum Ratings by Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 M29FxGxxxAC 3V Device DC and Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 M29FxGxxxBC 1.8V Device DC and Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .43 Valid Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 AC Characteristics: Command, Data, and Address Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 AC Characteristics: Normal Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 PROGRAM/ERASE Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
www..net
PDF: 09005aef814b01a2 / Source: 09005aef814b01c7 2_4_8gb_nand_m49aLOT.fm - Rev. A 3/06 EN
6
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved.
2Gb, 4GB, 8Gb: x8, x16 NAND Flash Memory General Description
General Description
NAND Flash technology provides a cost-effective solution for applications requiring high-density solid-state storage. Micron MT29F2G08AxC and MT29F2G16AxC devices are 2Gb NAND Flash memory devices. The MT29F4G08BxC and MT29F4G16BxC are 4Gb devices. The MT29F8G08FAC is a four-die stack that operates as two independent 4Gb devices, providing a total storage capacity of 8Gb in a single, space-saving package. These devices include standard NAND features as well as new features designed to enhance system-level performance. Micron NAND Flash devices use a highly multiplexed 8- or 16-bit bus (I/O[7:0] or I/O[15:0]) to transfer data, addresses, and instructions. The five command pins (CLE, ALE, CE#, RE#, WE#) implement the NAND command bus interface protocol. Three additional pins control hardware write protection (WP#), monitor device status (R/B#), and initiate the power-on AUTO-READ (PRE) feature. The PRE function is available on 3V commercial-temperature devices only. This hardware interface creates a low-pin-count device with a standard pinout that is the same from one density to another, supporting future upgrades to higher densities without board redesign. The MT29F2G and MT29F4G devices contain 2,048 and 4,096 erasable blocks respectively. Each block is subdivided into 64 programmable pages. Each page consists of 2,112 bytes (x8) or 1,056 words (x16). The pages are further divided into a 2,048-byte data storage region with a separate 64-byte area on the x8 device; and on the x16 device, separate 1,024-word and 32-word areas. The 64-byte and 32-word areas are typically used for error management functions. The contents of each 2,112-byte page can be programmed in 300s, and an entire 132Kbyte/66K-word block can be erased in 2ms. On-chip control logic automates PROGRAM and ERASE operations to maximize cycle endurance. ERASE/PROGRAM endurance is specified at 100K cycles when using appropriate error correcting code (ECC) and error management. Figure 3: NAND Flash Functional Block Diagram
VCC
www..net
VSS
I/O [7:0] I/O [15:0]
I/O Control
Address Register Status Register
Command Register CE# CLE ALE RE# WP# PRE (3V I/O only) R/B# Row Decode Data Register Cache Register WE# Control Logic Column Decode
Note:
PDF: 09005aef814b01a2 / Source: 09005aef814b01c7 2_4_8gb_nand_m49a__2.fm - Rev. A 3/06 EN
The PRE function is not supported on extended-temperature devices.
7
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved.
2Gb, 4GB, 8Gb: x8, x16 NAND Flash Memory General Description
Figure 4:
x16
48-Pin TSOP Type 1 Pin Assignments (Top View)
x8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 x8
NC NC NC NC I/O7 I/O6 I/O5 I/O4 NC NC PRE2 VCC VSS NC NC NC I/O3 I/O2 I/O1 I/O0 NC NC NC NC
x16
VSS I/O15 I/O7 I/O14 I/O6 I/O13 I/O5 I/O12 I/O4 NC PRE2 VCC NC NC NC I/O11 I/O3 I/O10 I/O2 I/O9 I/O1 I/O8 I/O0 VSS
NC NC NC NC NC NC NC NC NC NC R/B2#1 R/B2#1 R/B# R/B# RE# RE# CE# CE# CE2#1 CE2#1 NC NC VCC VCC VSS VSS NC NC NC NC CLE CLE ALE ALE WE# WE# WP# WP# DNU DNU DNU DNU DNU DNU NC NC NC NC
Notes: 1. R/B2# and CE2# are only available on 8Gb devices. These pins are NC for other configurations. 2. The PRE function is available on 3V commercial-temperature devices. The PRE pin can be left unconnected if not in use, in which case, PRE functionality is disabled.
www..net
PDF: 09005aef814b01a2 / Source: 09005aef814b01c7 2_4_8gb_nand_m49a__2.fm - Rev. A 3/06 EN
8
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved.
2Gb, 4GB, 8Gb: x8, x16 NAND Flash Memory General Description
Table 1: Pin/Pad Descriptions
Type Input Description Address latch enable: During the time ALE is HIGH, address information is transferred from I/O[7:0] into the on-chip address register upon a LOW-to-HIGH transition on WE#. When address information is not being loaded, the ALE pin should be driven LOW. Chip enable: Gates transfers between the host system and the NAND Flash device. Once the device starts a PROGRAM or ERASE operation, the chip enable pin can be de-asserted. For the 8Gb configuration, CE# controls the first 4Gb of memory; CE2# controls the second 4Gb. See "Bus Operation" on page 17 for additional operational details. In the 8Gb configuration, R/B# is for the 4Gb of memory enabled by CE#; R/B2# is for the 4Gb of memory enabled by the CE2#. Command latch enable: When CLE is HIGH, information is transferred from I/O[7:0] to the on-chip command register on the rising edge of WE#. When command information is not being loaded, CLE should be driven LOW. Power-on auto-read enable: When PRE is HIGH, the power-on AUTO-READ function is enabled. To disable this function, connect PRE to Vss, or leave it unconnected. The power-on AUTO-READ function is available on 3V commercialtemperature devices. On the MT29F8G08FAC, the PRE function is available only on the 4Gb of memory controlled by CE#. PRE is not available on the 4Gb of memory controlled by CE2#. Read enable: Gates transfers from the NAND Flash device to the host system. Write enable: Gates transfers from the host system to the NAND Flash device. Write protect: Pin protects against inadvertent PROGRAM and ERASE operations. All PROGRAM and ERASE operations are disabled when the WP# pin is LOW. Data inputs/outputs: The bidirectional I/O pins transfer address, data, and instruction information. Data is output only during READ operations; at other times the I/O pins are inputs.
Symbol ALE
CE#, CE2#
Input
CLE
Input
PRE
Input
RE# WE# WP# I/O[7:0] MT29FxG08 I/O[15:0] MT29FxG16 R/B#, R/B2#
www..net
Input Input Input I/O
Output
VCC VSS NC DNU
Supply Supply - -
Ready/busy: An open-drain, active-LOW output that uses an external pull-up resistor, the pin is used to indicate when the chip is processing a PROGRAM or ERASE operation. The pin is also used during a READ operation to indicate when data is being transferred from the array into the serial data register. Once these operations have completed, the R/B# returns to the High-Z state. VCC: Power supply. VSS: Ground connection. No connect: NC pins are not internally connected. These pins can be driven or left unconnected. Do not use: These pins must be left unconnected.
PDF: 09005aef814b01a2 / Source: 09005aef814b01c7 2_4_8gb_nand_m49a__2.fm - Rev. A 3/06 EN
9
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved.
2Gb, 4GB, 8Gb: x8, x16 NAND Flash Memory Architecture
Architecture
These devices use NAND Flash electrical and command interfaces. Data, commands, and addresses are multiplexed onto the same pins to provide a memory device with a low pin count. The internal memory array is accessed on a page basis. When doing reads, a page of data is copied from the memory array into the data register. Once copied to the data register, data is output sequentially, byte-by-byte on x8 devices, or word-by-word on x16 devices. The memory array is programmed on a page basis. After the starting address is loaded into the internal address register, data is sequentially written to the internal data register up to the end of a page. After all of the page data has been loaded into the data register, array programming is started. In order to increase programming bandwidth, this device incorporates a cache register. In the cache programming mode, data is first copied into the cache register and then into the data register. Once the data is copied into the data register, programming begins. After the data register has been loaded and programming started, the cache register becomes available for loading additional data. Loading the next page of data into the cache register takes place while page programming is in process. The INTERNAL DATA MOVE command also uses the internal cache register. Normally, moving data from one area of external memory to another uses a large number of external memory cycles. By using the internal cache register and data register, array data can be copied from one page and then programmed into another without using external memory cycles.
Addressing
NAND Flash devices do not contain dedicated address pins. Addresses are loaded using a five-cycle sequence as shown in Tables 4 and 5 on pages 13 and 14, respectively. See Figures 5 and 6 on pages 11 and 12 for additional memory mapping and addressing details.
www..net
PDF: 09005aef814b01a2 / Source: 09005aef814b01c7 2_4_8gb_nand_m49a__2.fm - Rev. A 3/06 EN
10
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved.
2Gb, 4GB, 8Gb: x8, x16 NAND Flash Memory Memory Mapping
Memory Mapping
Figure 5: Memory Map x8
0 1 2 * * * * * * * * * * * * 2,047
Blocks BA[16:6]
Pages PA[5:0]
0
1
2
***
63
Bytes CA[11:0]
0
1
2
*******************
2,047
***
2,111
Spare area
Table 2:
Block 0 0 0 ... 2,046 2,047
www..net
Operational Example (x8)
Page 0 1 2 ... 62 63 Min Address in Page 0x0000000000 0x0000010000 0x0000020000 ... 0x01FFFE0000 0x01FFFF0000 Max Address in Page 0x000000083F 0x000001083F 0x000002083F ... 0x01FFFE083F 0x01FFFF083F Out of Bounds Addresses in Page 0x0000000840-0x0000000FFF 0x0000010840-0x0000010FFF 0x0000020840-0x0000020FFF 0x01FFFE0840-0x01FFFE0FFF 0x01FFFF0840-0x01FFFF0FFF
Notes: 1. As shown in Table 4 on page 13, the high nibble of ADDRESS cycle 2 has no assigned address bits; however, these 4 bits must be held LOW during the ADDRESS cycle to ensure that the address is interpreted correctly by the NAND Flash device. These extra bits are accounted for in ADDRESS cycle 2 even though they do not have address bits assigned to them. 2. The 12-bit column address is capable of addressing from 0 to 4,095 bytes on x8 devices; however, only bytes 0 through 2,111 are valid. Bytes 2,112 through 4,095 of each page are "out of bounds," do not exist in the device, and cannot be addressed.
PDF: 09005aef814b01a2 / Source: 09005aef814b01c7 2_4_8gb_nand_m49a__2.fm - Rev. A 3/06 EN
11
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved.
2Gb, 4GB, 8Gb: x8, x16 NAND Flash Memory Memory Mapping
Figure 6: Memory Map x16
Blocks BA[16:6]
0
1
2
* * * * * * * * * * * * 2,047
Pages PA[5:0]
0
1
2
***
63
Words CA[10:0]
0
1
2
*******************
1,023
***
1,055
Spare area
Table 3:
Block 0 0 0 ... 2,046 2,047
Operational Example (x16)
Page 0 1 2 ... 62 63 Min Address in Page 0x0000000000 0x0000010000 0x0000020000 ... 0x01FFFE0000 0x01FFFF0000 Max Address in Page 0x000000041F 0x000001041F 0x000002041F ... 0x01FFFE041F 0x01FFFF041F Out of Bounds Addresses in Page 0x0000000420-0x0000000FFF 0x0000010420-0x0000010FFF 0x0000020420-0x0000020FFF 0x01FFFE0420-0x01FFFE0FFF 0x01FFFF0420-0x01FFFF0FFF
www..net
Notes: 1. As shown in Table 5 on page 14, the upper 5 bits of ADDRESS cycle 2 have no assigned address bits; however, these 5 bits must be held LOW during the ADDRESS cycle to ensure that the address is interpreted correctly by the NAND Flash device. These extra bits are accounted for in ADDRESS cycle 2 even though they do not have address bits assigned to them. 2. The 11-bit column address is capable of addressing from 0 to 2,047 bytes on x16 devices; however, only bytes 0 through 1,055 are valid. Bytes 1,056 through 2,048 of each page are "out of bounds," do not exist in the device, and cannot be addressed.
PDF: 09005aef814b01a2 / Source: 09005aef814b01c7 2_4_8gb_nand_m49a__2.fm - Rev. A 3/06 EN
12
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved.
2Gb, 4GB, 8Gb: x8, x16 NAND Flash Memory Memory Mapping
Figure 7: Array Organization for MT29F2G08AxC (x8)
2,112 bytes
I/O 0 Cache Register Data Register
2,048 2,048
64 64
I/O 7
2,048 blocks per device
1 Block
64 pages = 1 block (128K + 4K) bytes 1 page 1 block = (2K + 64) bytes = (2K + 64) bytes x 64 pages = (128K + 4K) bytes
1 device = (2K + 64) bytes x 64 pages x 2,048 blocks = 2,112Mb
Table 4:
Cycle First Second Third Fourth Fifth
Array Addressing: MT29F2G08AxC
I/O7 CA7 LOW BA7 BA15 LOW I/O6 CA6 LOW BA6 BA14 LOW I/O5 CA5 LOW PA5 BA13 LOW I/O4 CA4 LOW PA4 BA12 LOW I/O3 CA3 CA111 PA3 BA11 LOW I/O2 CA2 CA10 PA2 BA10 LOW I/O1 CA1 CA9 PA1 BA9 LOW I/O0 CA0 CA8 PA0 BA8 BA16
www..net
Notes: 1. If CA11 = "1" then CA[10:6] must be "0." 2. Block address concatenated with page address = actual page address; CAx = column address; PAx = page address, BAx = block address
PDF: 09005aef814b01a2 / Source: 09005aef814b01c7 2_4_8gb_nand_m49a__2.fm - Rev. A 3/06 EN
13
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved.
2Gb, 4GB, 8Gb: x8, x16 NAND Flash Memory Memory Mapping
Figure 8: Array Organization for MT29F2G16AxC (x16)
1,056 words
I/O 0 Cache Register Data Register
1,024 1,024
32 32
I/O 15
2,048 blocks per device
1 Block
64 pages = 1 block (64K + 2K) words 1 page 1 block = (1K + 32) words = (1K + 32) words x 64 pages = (64K + 2K) words
1 device = (1K + 32) words x 64 pages x 2,048 blocks = 2,112Mb
Note:
For x16 devices, contact factory.
Table 5:
Cycle First Second Third Fourth Fifth
Array Addressing: MT29F2G16AxC
I/O[15:8] LOW LOW LOW LOW LOW I/O7 CA7 LOW BA7 BA15 LOW I/O6 CA6 LOW BA6 BA14 LOW I/O5 CA5 LOW PA5 BA13 LOW I/O4 CA4 LOW PA4 BA12 LOW I/O3 CA3 LOW PA3 BA11 LOW I/O2 CA2 CA101 PA2 BA10 LOW I/O1 CA1 CA9 PA1 BA9 LOW I/O0 CA0 CA8 PA0 BA8 BA16
www..net
Notes: 1. If CA10 = "1" then CA[9:5] must be "0." 2. Block address concatenated with page address = actual page address. CAx = column address; PAx = page address, BAx = block address. 3. I/O[15:8] are not used during the addressing sequence and should be driven LOW.
PDF: 09005aef814b01a2 / Source: 09005aef814b01c7 2_4_8gb_nand_m49a__2.fm - Rev. A 3/06 EN
14
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved.
2Gb, 4GB, 8Gb: x8, x16 NAND Flash Memory Memory Mapping
Figure 9: Array Organization for MT29F4G08BxC and MT29F8G08FxC (x8)
2,112 bytes
I/O 0 Cache Register Data Register
2,048 2,048
64 64
I/O 7
4,096 blocks per device
1 Block
64 pages = 1 block (128K + 4K) bytes 1 page 1 block = (2K + 64) bytes = (2K + 64) bytes x 64 pages = (128K + 4K) bytes
1 device = (2K + 64) bytes x 64 pages x 4,096 blocks = 4,224Mb
Note:
For the 8Gb MT29F8G08F, the 4Gb array organization shown here applies to each chip enable (CE# and CE2#).
Table 6:
Cycle First Second Third Fourth Fifth
www..net
Array Addressing for MT29F4G08BxC and MT29F8G08FxC (x8)
I/O7 CA7 LOW BA7 BA15 LOW I/O6 CA6 LOW BA6 BA14 LOW I/O5 CA5 LOW PA5 BA13 LOW I/O4 CA4 LOW PA4 BA12 LOW I/O3 CA3 CA111 PA3 BA11 LOW I/O2 CA2 CA10 PA2 BA10 LOW I/O1 CA1 CA9 PA1 BA9 BA172 I/O0 CA0 CA8 PA0 BA8 BA16
Notes: 1. If CA11 = "1" then CA[10:6] must be "0." 2. Die address boundary: "0" = 0Gb-2Gb devices, "1" = 2Gb-4Gb devices. 3. Block address concatenated with page address = actual page address. CAx = column address; PAx = page address, BAx = block address.
PDF: 09005aef814b01a2 / Source: 09005aef814b01c7 2_4_8gb_nand_m49a__2.fm - Rev. A 3/06 EN
15
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved.
2Gb, 4GB, 8Gb: x8, x16 NAND Flash Memory Memory Mapping
Figure 10: Array Organization for MT28F4G16BxC and MT29F8G16FxC (x16)
1,056 words
I/O 0 Cache Register Data Register
1,024 1,024
32 32
I/O 15
4,096 blocks per device
1 Block
64 pages = 1 block (64K + 2K) words 1 page 1 block = (1K + 32) words = (1K + 32) words x 64 pages = (64K + 2K) words
1 device = (1K + 32) words x 64 pages x 4,096 blocks = 4,224Mb
Notes: 1. For x16 devices, contact factory. 2. For the 8Gb MT29F8G16F, the 4Gb array organization shown here applies to each chip enable (CE# and CE2#).
Table 7:
Cycle First Second Third Fourth Fifth
www..net
Array Addressing for MT28F4G16BxC and MT29F8G16FxC (x16)
I/O[15:8] LOW LOW LOW LOW LOW I/O7 CA7 LOW BA7 BA15 LOW I/O6 CA6 LOW BA6 BA14 LOW I/O5 CA5 LOW PA5 BA13 LOW I/O4 CA4 LOW PA4 BA12 LOW I/O3 CA3 LOW PA3 BA11 LOW I/O2 CA2 CA101 PA2 BA10 LOW I/O1 CA1 CA9 PA1 BA9 BA172 I/O0 CA0 CA8 PA0 BA8 BA16
Notes: 1. If CA10 = "1" then CA[9:5] must be "0." 2. Die address boundary: "0" = 0Gb-2Gb devices, "1" = 2Gb-4Gb devices. 3. Block address concatenated with page address = actual page address. CAx = column address; PAx = page address, BAx = block address. 4. I/O[15:8] are not used during the addressing sequence and should be driven LOW.
PDF: 09005aef814b01a2 / Source: 09005aef814b01c7 2_4_8gb_nand_m49a__2.fm - Rev. A 3/06 EN
16
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved.
2Gb, 4GB, 8Gb: x8, x16 NAND Flash Memory Bus Operation
Bus Operation
The bus on the MT29Fxxx devices is multiplexed. Data I/O, addresses, and commands all share the same pins. I/O pins I/O[15:8] are used only for data in the x16 configuration. Addresses and commands are always supplied on I/O[7:0]. The command sequence normally consists of a command latch cycle, an ADDRESS LATCH cycle, and a DATA cycle--either READ or WRITE.
Control Signals
CE#, WE#, RE#, CLE, ALE and WP# control NAND Flash device READ and WRITE operations. On the 8Gb MT29F8G08FAC, CE# and CE2# each control independent 4Gb arrays. CE2# functions the same as CE# for its own array; all operations described for CE# also apply to CE2#. CE# is used to enable the device. When CE# is LOW and the device is not in the busy state, the NAND Flash memory will accept command, data, and address information. When the device is not performing an operation, CE# is typically driven HIGH and the device enters standby mode. The memory will enter standby if CE# goes HIGH while data is being transferred and the device is not busy. This helps reduce power consumption. See Figure 43 on page 49 and Figure 51 on page 55 for examples of CE# "Don't Care" operations. The CE# "Don't Care" operation enables the NAND Flash to reside on the same asynchronous memory bus as other Flash or SRAM devices. Other devices on the memory bus can then be accessed while the NAND Flash is busy with internal operations. This capability is important for designs that require multiple NAND devices on the same bus. One device can be programmed while another is being read. A HIGH CLE signal indicates that a command cycle is taking place. A HIGH ALE signal signifies that an address input cycle is occurring.
Commands
Commands are written to the command register on the rising edge of WE# when: * CE# and ALE are LOW, and * CLE is HIGH, and * the device is not busy. The exceptions to this are the READ STATUS and RESET commands when busy. See Figure 37 on page 46 for detailed timing requirements. Commands are input on I/O[7:0] only. For devices with a x16 interface, I/O[15:8] must be written with zeros when issuing a command.
www..net
Address Input
Addresses are written to the address register on the rising edge of WE# when: * CE# and CLE are LOW, and * ALE is HIGH, and * the device is not busy. Addresses are input on I/O[7:0] only; bits not part of the address space must be LOW. For devices with a x16 interface, I/O[15:8] must be written with zeros when issuing an address. The number of ADDRESS cycles required for each command varies. Refer to the command descriptions to determine addressing requirements. (See Table 9 on page 22.)
PDF: 09005aef814b01a2 / Source: 09005aef814b01c7 2_4_8gb_nand_m49a__2.fm - Rev. A 3/06 EN
17
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved.
2Gb, 4GB, 8Gb: x8, x16 NAND Flash Memory Bus Operation Data Input
Data is written to the data register on the rising edge of WE# when: * CE#, CLE, and ALE are LOW, and * the device is not busy. Data is input on I/O[7:0] for x8 devices, and I/O[15:0] on x16 devices. See Figure 39 on page 47 for additional data input details.
READs
After a READ command is issued, data is transferred from the memory array to the data register on the rising edge of WE#. R/B# goes LOW for tR and transitions HIGH after the transfer is complete. When R/B# goes HIGH, data is available in the data register, and is clocked out of the part by toggling RE#. See Figure 42 on page 48 for detailed timing information. The READ STATUS (70h) command or the R/B# signal can be used to determine when the device is ready. See the READ STATUS command section on page 28 for details.
Ready/Busy#
The R/B# output provides a hardware method of indicating the completion of PROGRAM, ERASE, and READ operations. The signal requires a pull-up resistor for proper operation. The signal is typically HIGH, and transitions to LOW after the appropriate command is written to the device. The signal pin's open-drain driver enables multiple R/B# outputs to be OR-tied. The READ STATUS command can be used in place of R/B#. Typically R/B# is connected to an interrupt pin on the system controller (see Figure 13 on page 19). On the 8Gb MT29F8G08FAC, R/B# provides a status indication for the 4Gb section enabled by CE#, and R/B2# does the same for the 4Gb section enabled by CE2#. R/B# and R/B2# can be tied together, or they can be used separately to provide independent indications for each 4Gb section. The combination of Rp and capacitive loading of the R/B# circuit determines the rise time of the R/B# pin. The actual value used for Rp depends on the system timing requirements. Large values of Rp cause R/B# to be delayed significantly. At the 10- to 90-percent points on the R/B# waveform, rise time is approximately two time constants (TC). Time Constants
TC = R x C Where R = Rp (resistance of pull-up resistor), and C = total capacitive load.
www..net
Figure 11:
The fall time of the R/B# signal is determined mainly by the output impedance of the R/B# pin and the total load capacitance. Refer to Figure 14 on page 19, and Figure 15 on page 20, which depict approximate Rp values using a circuit load of 100pF. The minimum value for Rp is determined by the output drive capability of the R/B# signal, the output voltage swing, and VCC.
PDF: 09005aef814b01a2 / Source: 09005aef814b01c7 2_4_8gb_nand_m49a__2.fm - Rev. A 3/06 EN
18
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved.
2Gb, 4GB, 8Gb: x8, x16 NAND Flash Memory Bus Operation
Figure 12: Minimum Rp
VCC (MAX) - VOL (MAX) Rp (MIN, 1.8V part) = IOL + IL VCC (MAX) - VOL (MAX) Rp (MIN, 3.3V part) = IOL + IL = = 1.85V 3mA + IL 3.2V 8mA + IL
Where IL is the sum of the input currents of all devices tied to the R/B# pin.
Figure 13:
READY/BUSY# Open Drain
Rp VCC
R/B# Open drain output
IOL
GND Device
Figure 14:
www..net
t
Fall and tRise
3.50 3.00 2.50 2.00 V 1.50 1.00 0.50 0.00 -1 0 2 4 TC 0 2 4 6
Vcc 3.3 Vcc 1.8
tFall
tRise
Notes: 1. 2. 3.
and tRise calculated at 10 percent and 90 percent points. primarily dependent on external pull-up resistor and external capacitive loading. tFall 10ns at 3.3V; tFall 7ns at 1.8V.
tRise
tFall
PDF: 09005aef814b01a2 / Source: 09005aef814b01c7 2_4_8gb_nand_m49a__2.fm - Rev. A 3/06 EN
19
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved.
2Gb, 4GB, 8Gb: x8, x16 NAND Flash Memory Bus Operation
Figure 15: IOL vs. Rp
3.50 3.00 2.50 2.00
T (s)
1.50 1.00 0.50 0.00 0 2,000 4,000 6,000 8,000 10,000 12,000
Rp ()
IOL at 3.60V (mA) IOL at 1.95V (mA)
Table 8:
CLE H L H L L
www..net
Mode Selection
ALE L H L H L L L X X X X CE# L L L L L L L X X X H H H X X X X H X X X X WE# RE# H H H H H WP#1 X X H H H X X H H L 0V/Vcc PRE2 X X X X X X X X X X 0V/Vcc Data input Sequential read and data output During read (busy) During program (busy) During erase (busy) Write protect Standby Write mode Mode Read mode Command input Address input Command input Address input
L L X X X X
Notes: 1. WP# should be biased to CMOS HIGH or LOW for standby. 2. Do not transition PRE during device operations. PRE is only supported on 3V devices and can be left unconnected if not used. PRE is not supported on extended-temperature devices. 3. H = Logic level HIGH; L = Logic level LOW; X = VIH or VIL
PDF: 09005aef814b01a2 / Source: 09005aef814b01c7 2_4_8gb_nand_m49a__2.fm - Rev. A 3/06 EN
20
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved.
2Gb, 4GB, 8Gb: x8, x16 NAND Flash Memory Bus Operation Power-On AUTO-READ
During power-on, with the PRE pin at VCC, 3V devices automatically transfer the first page of the memory array to the data register without requiring a command or addressinput sequence. After VCC reaches approximately 2.5V, the internal voltage detector initiates the power-on AUTO-READ function. R/B# will stay LOW (tRPRE) while the first page of data is copied into the data register. See Table 21 on page 45 for tRPRE values. Once the READ is complete and R/B# goes HIGH, RE# can be toggled repeatedly to output the first page of data. If connected, PRE must be set to 0V or VCC at power-on, and must not be toggled during device operations. PRE can be left unconnected if not used, in which case, PRE functionality is disabled. The power-on AUTO-READ function is available only on 3V commercial-temperature devices. Figure 16: First Page Power-On AUTO-READ (3V devices only)
2.5V1 Vcc
CLE
CE#
WE#
ALE
PRE
tRPRE
R/B#
RE#
www..net
I/Ox
1st
2nd
3rd
.....
n th
Undefined
Notes: 1. Verified per device characterization; not 100 percent tested on all devices.
PDF: 09005aef814b01a2 / Source: 09005aef814b01c7 2_4_8gb_nand_m49a__2.fm - Rev. A 3/06 EN
21
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved.
2Gb, 4GB, 8Gb: x8, x16 NAND Flash Memory Command Definitions
Command Definitions
Table 9: Command Set
Command Cycle 1 00h 31h 3Fh 00h 05h 90h 70h 80h 80h 85h 85h 60h FFh A0h A5h AFh Number of Address Cycles 5 - - 5 2 1 - 5 5 5 2 3 - 5 5 5 Data Cycles Required1 No No No No No No No Yes Yes Optional Yes No No Yes No No Command Cycle 2 30h - - 35h E0h - - 10h 15h 10h - D0h - 10h 10h 30h Valid During Busy No No No No No No Yes No No No No No Yes No No No
Operation PAGE READ PAGE READ CACHE MODE START PAGE READ CACHE MODE START LAST READ for INTERNAL DATA MOVE RANDOM DATA READ READ ID READ STATUS PROGRAM PAGE PROGRAM PAGE CACHE MODE PROGRAM for INTERNAL DATA MOVE RANDOM DATA INPUT BLOCK ERASE RESET OTP DATA PROGRAM OTP DATA PROTECT OTP DATA READ
Notes
2 3
2 4
Notes: 1. Indicates required data cycles between command cycle 1 and command cycle 2. 2. Do not cross die boundaries when using READ for INTERNAL DATA MOVE and PROGRAM for INTERNAL DATA MOVE. 3. RANDOM DATA READ command limited to use within a single page. 4. RANDOM DATA INPUT command limited to use within a single page.
www..net
PDF: 09005aef814b01a2 / Source: 09005aef814b01c7 2_4_8gb_nand_m49a__2.fm - Rev. A 3/06 EN
22
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved.
2Gb, 4GB, 8Gb: x8, x16 NAND Flash Memory Command Definitions READ Operations
PAGE READ 00h-30h On initial power up, the device defaults to read mode. To enter the read mode while in operation, write the 00h command to the command register, then write five ADDRESS cycles followed by the 30h command. To determine the progress of the data transfer from the NAND Flash array to the data register (tR), monitor the R/B# signal; or alternately, issue a READ STATUS (70h) command. If the READ STATUS command is used to monitor the data transfer, the user must re-issue the READ (00h) command to receive data output from the data register. See Figure 47 on page 52 and Figure 48 on page 53 for examples. After the READ command has been re-issued, pulsing the RE# line will result in outputting data, starting from the initial column address. A serial page read sequence outputs a complete page of data. After 30h is written, the page data is transferred to the data register, and R/B# goes LOW during the transfer. When the transfer to the data register is complete, R/B# returns HIGH. At this point, data can be read from the device. Starting from the initial column address to the end of the page, read the data by repeatedly pulsing RE# at the maximum tRC rate (see Figure 17). Figure 17:
CLE
tCLR
PAGE READ Operation
CE#
tWC
WE#
tWB tAR
ALE
www..net
tR
tRC
tRHZ
RE#
tRR tRP DOUT N DOUT N+1 DOUT M
I/Ox
00h
Col Add 1
Col Add 2
Row Add 1
Row Add 2
Row Add 3
30h
Busy
R/B# Don't Care
PDF: 09005aef814b01a2 / Source: 09005aef814b01c7 2_4_8gb_nand_m49a__2.fm - Rev. A 3/06 EN
23
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved.
2Gb, 4GB, 8Gb: x8, x16 NAND Flash Memory Command Definitions
RANDOM DATA READ 05h-E0h The RANDOM DATA READ command enables the user to specify a new column address so the data at single or multiple addresses can be read. The random read mode is enabled after a normal PAGE READ (00h-30h) sequence. Random data can be output after the initial page read by writing an 05h-E0h command sequence along with the new column address (two cycles). The RANDOM DATA READ command can be issued without limit within the page. Only data on the current page can be read. Pulsing the RE# pin outputs data sequentially (see Figure 18). Figure 18: RANDOM DATA READ Operation
tR R/B#
RE#
I/Ox
00h
Address (5 Cycles)
30h
Data Output
05h
Address (2 Cycles)
E0h
Data Output
PAGE READ CACHE MODE Start 31h; PAGE READ CACHE MODE Start Last 3Fh Micron NAND Flash devices have a cache register that can be used to increase the READ operation speed when accessing sequential pages in a block. First, a normal PAGE READ (00h-30h) command sequence is issued. See Figure 19 on page 25 for operation details. The R/B# signal goes LOW for tR during the time it takes to transfer the first page of data from the memory to the data register. After R/B# returns to HIGH, the PAGE READ CACHE MODE START (31h) command is latched into the command register. R/B# goes LOW for tDCBSYR1 while data is being transferred from the data register to the cache register. Once the data register contents are transferred to the cache register, another PAGE READ is automatically started as part of the 31h command. Data is transferred from the next sequential page of the memory array to the data register during the same time data is being read serially (pulsing of RE#) from the cache register. If the total time to output data exceeds tR, then the PAGE READ is hidden. The second and subsequent pages of data are transferred to the cache register by issuing additional 31h commands. R/B# will stay LOW up to tDCBSYR2. This time can vary, depending on whether the previous memory-to-data-register transfer was completed prior to issuing the next 31h command. See Table 21 on page 45 for timing parameters. If the data transfer from memory to the data register is not completed before the 31h command is issued, R/B# stays LOW until the transfer is complete. It is not necessary to output a whole page of data before issuing another 31h command. R/B# will stay LOW until the previous PAGE READ is complete and the data has been transferred to the cache register. To read out the last page of data, the PAGE READ CACHE MODE START LAST (3Fh) command is issued. This command transfers data from the data register to the cache register without issuing another PAGE READ (see Figure 19 on page 25).
www..net
PDF: 09005aef814b01a2 / Source: 09005aef814b01c7 2_4_8gb_nand_m49a__2.fm - Rev. A 3/06 EN
24
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved.
2Gb, 4GB, 8Gb: x8, x16 NAND Flash Memory Command Definitions
tDCBSYR2
3Fh
tDCBSYR2
31h
PAGE READ CACHE MODE
tR
Figure 19:
PDF: 09005aef814b01a2 / Source: 09005aef814b01c7 2_4_8gb_nand_m49a__2.fm - Rev. A 3/06 EN
WE#
R/B#
I/Ox
CLE
CE#
ALE
RE#
00h
Address (5 Cycles)
30h
31h
www..net
tDCBSYR1
25
(Serial Access)
Data Output
(Serial Access)
Data Output
(Serial Access)
Data Output
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved.
Don't Care
2Gb, 4GB, 8Gb: x8, x16 NAND Flash Memory Command Definitions
READ ID 90h The READ ID (90h) command is used to read the 4 bytes of identifier codes programmed into the devices. The READ ID command reads a 4-byte table that includes manufacturer ID, device configuration, and part-specific information. (See Table 10 on page 27.) Writing 90h to the command register puts the device into the read ID mode. The command register stays in this mode until another valid command is issued (see Figure 20). Figure 20:
CLE
READ ID Operation
CE#
WE#
tAR
ALE
RE#
tWHR tREA Byte 0 Byte 1 Byte 2 Byte 3
I/Ox
90h
00h Address, 1 Cycle
Notes: 1. See Table 10 on page 27 for byte definitions.
www..net
PDF: 09005aef814b01a2 / Source: 09005aef814b01c7 2_4_8gb_nand_m49a__2.fm - Rev. A 3/06 EN
26
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved.
2Gb, 4GB, 8Gb: x8, x16 NAND Flash Memory Command Definitions
Table 10: Device ID and Configuration Codes
Options Byte 0 Byte 1 MT29F2G08AAC MT29F2G08ABC MT29F2G16AAC MT29F2G16ABC MT29F4G08BAC MT29F8G08FAC Byte 2 Byte value Byte 3 Page size Spare area size (bytes) Block size (w/o spare) Organization Reserved Byte value Manufacturer ID Micron Device ID 2Gb, x8, 3V 2Gb, x8, 1.8V 2Gb, x16, 3V 2Gb, x16, 1.8V 4Gb, x8, 3V 8Gb, x8, 3V Don't Care 2KB 64 128KB x8 x16 x8 x16 0 0 0 I/O7 0 1 1 1 1 1 1 x I/O6 0 1 0 1 0 1 1 x I/O5 1 0 1 0 1 0 0 x I/O4 0 1 0 0 1 1 1 x I/O3 1 1 1 1 1 1 1 x I/O2 1 0 0 0 0 1 1 x I/O1 0 1 1 1 1 0 0 x 0 0 0 0 1 0 1 0 0 1 1 0 0 1 1 0 0 1 1 1 1 I/O0 0 0 0 0 0 0 0 x 1 Value1 2Ch DAh AAh CAh BAh DCh DCh XXh 01b 01b 01b 0b 1b 0b 15h 55h Notes
2 2 2 3
Notes: 1. b = binary; h = hex. 2. Device IDs for these configurations are provided for reference only. 3. The MT29F8G08FAC device ID code reflects the configuration of each 4Gb section.
w
w
w
.
D
a
t
a
S
h
e
e
t
4
U
.
n
e
t
PDF: 09005aef814b01a2 / Source: 09005aef814b01c7 2_4_8gb_nand_m49a__2.fm - Rev. A 3/06 EN
27
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved.
2Gb, 4GB, 8Gb: x8, x16 NAND Flash Memory Command Definitions
READ STATUS 70h NAND Flash devices have an 8-bit status register that the software can read during device operation. On the x16 device, I/O[15:8] are "0" when reading the status register. Table 11 describes the status register. After a READ STATUS command, all READ cycles will be from the status register until a new command is issued. Changes in the status register will be seen on I/O[7:0] as long as CE# and RE# are LOW; it is not necessary to start a new READ STATUS cycle to see these changes. While monitoring the read status to determine when the tR (transfer from NAND Flash array to data register) is complete, the user must re-issue the READ (00h) command to make the change from status mode to read mode. After the READ command has been re-issued, pulsing the RE# line will result in outputting data, starting from the initial column address. Table 11:
SR Bit 0 1 2 3 4 5 6 7 [15:8]
Status Register Bit Definition
Program Page Cache Mode Pass/fail (N) Pass/fail (N-1) - - - Ready/busy1 Ready/busy cache2 Write protect - Page Read - - - - - Ready/busy Ready/busy Page Read Cache Mode - - - - - Ready/busy1 Block Erase Pass/fail Definition
Page Program Pass/fail - - - - Ready/busy Ready/busy Write protect -
Ready/busy cache2 Write protect Write protect - -
"0" = Successful PROGRAM/ERASE "1" = Error in PROGRAM/ERASE - "0" = Successful PROGRAM/ERASE "1" = Error in PROGRAM/ERASE - "0" - "0" - "0" Ready/busy "0" = Busy "1" = Ready Ready/busy "0" = Busy "1" = Ready Write protect "0" = Protected "1" = Not protected - "0"
www..net
Notes: 1. Status register bit 5 is "0" during the actual programming operation. If cache mode is used, this bit will be "1" when all internal operations are complete. 2. Status register bit 6 is "1" when the cache is ready to accept new data. R/B# follows bit 6. See Figure 19 on page 25, and Figure 24 on page 30.
Figure 21:
CE#
Status Register Operation
tCLR CLE
WE# tREA RE#
I/Ox
70h
Status Output
PDF: 09005aef814b01a2 / Source: 09005aef814b01c7 2_4_8gb_nand_m49a__2.fm - Rev. A 3/06 EN
28
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved.
2Gb, 4GB, 8Gb: x8, x16 NAND Flash Memory Command Definitions PROGRAM Operations
PROGRAM PAGE 80h-10h Micron NAND Flash devices are inherently page-programmed devices. Pages must be programmed consecutively within a block, from the least significant page address to the most significant page address (i.e., 0, 1, 2, ..., 63). Random page address programming is prohibited. Micron NAND flash devices also support partial-page programming operations. This means that any single bit can only be programmed one time before an erase is required; however, the page can be partitioned such that a maximum of eight programming operations are allowed before an erase is required. SERIAL DATA INPUT 80h PROGRAM PAGE operations require loading the SERIAL DATA INPUT (80h) command into the command register, followed by five ADDRESS cycles, then the data. Serial data is loaded on consecutive WE# cycles starting at the given address. The PROGRAM (10h) command is written after the data input is complete. The control logic automatically executes the proper algorithm and controls all the necessary timing to program and verify the operation. Write verification only detects "1s" that are not successfully written to "0s." R/B# goes LOW for the duration of array programming time, tPROG. The READ STATUS (70h) command and the RESET (FFh) command are the only commands valid during the programming operation. Bit 6 of the status register will reflect the state of R/B#. When the device reaches ready, read bit 0 of the status register to determine if the program operation passed or failed (see Figure 22). The command register stays in read status register mode until another valid command is written to it. RANDOM DATA INPUT 85h After the initial data set is input, additional data can be written to a new column address with the RANDOM DATA INPUT (85h) command. The RANDOM DATA INPUT command can be used any number of times in the same page prior to issuing the PAGE WRITE (10h) command. See Figure 23 for the proper command sequence. Figure 22:
www..net
PROGRAM and READ STATUS Operation
tPROG
R/B# 70h
I/Ox
80h
Address (5 Cycles)
DIN
10h
Status
I/O 0 = 0 PROGRAM successful I/O 0 = 1 PROGRAM error
Figure 23:
RANDOM DATA INPUT
tPROG
R/B# I/Ox
80h
Address (5 Cycles)
DIN
85h
Address (2 Cycles)
DIN
10h
70h
Status
PDF: 09005aef814b01a2 / Source: 09005aef814b01c7 2_4_8gb_nand_m49a__2.fm - Rev. A 3/06 EN
29
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved.
2Gb, 4GB, 8Gb: x8, x16 NAND Flash Memory Command Definitions
PROGRAM PAGE CACHE MODE 80h-15h Cache programming is actually a buffered programming mode of the standard PROGRAM PAGE command. Programming is started by loading the SERIAL DATA INPUT (80h) command to the command register, followed by five address cycles, and a full or partial page of data. The data is initially copied into the cache register, and the CACHE WRITE (15h) command is then latched to the command register. Data is transferred from the cache register to the data register on the rising edge of WE#. R/B# goes LOW during this transfer time. After the data has been copied into the data register and R/B# returns to HIGH, memory array programming begins. When R/B# returns to HIGH, new data can be written to the cache register by issuing another CACHE PROGRAM command sequence. The time that R/B# stays LOW will be controlled by the actual programming time. The first time through equals the time it takes to transfer the cache register contents to the data register. On the second and subsequent programming passes, transfer from the cache register to the data register is held off until current data register content has been programmed into the array. Bit 6 (cache R/B#) of the status register can be read by issuing the READ STATUS (70h) command to determine when the cache register is ready to accept new data. The R/B# pin always follows bit 6. Bit 5 (R/B#) of the status register can be polled to determine when the actual programming of the array is complete for the current programming cycle. If just the R/B# pin is used to determine programming completion, the last page of the program sequence must use the PROGRAM PAGE (10h) command instead of the CACHE PROGRAM (15h) command. If the CACHE PROGRAM (15h) command is used every time, including the last page of the programming sequence, status register bit 5 must be used to determine when programming is complete (see Figure 24). Bit 0 of the status register returns the pass/fail for the previous page when bit 6 of the status register is a "1" (ready state). The pass/fail status of the current PROGRAM operation is returned with bit 0 of the status register when bit 5 of the status register is a "1" (ready state) (see Figure 24). Figure 24: PROGRAM PAGE CACHE MODE Example
tCBSY
www..net
tCBSY
tCBSY
tLPROG1
R/B# I/Ox
80h Address/ Data Input 15h 80h Address/ Data Input 15h 80h Address/ Data Input 15h 80h Address/ Data Input 10h
A: Without status reads
tCBSY
tLPROG1
R/B# I/Ox
Address/ Data Input Status2 Output Address/ Data Input Status2 Output
80h
15h
70h
80h
10h
70h
B: With status reads
Notes: 1. See Note 3, Table 22 on page 45. 2. Check I/O[6:5] for internal ready/busy. Check I/O[1:0] for pass fail. RE# can stay LOW or pulse multiple times after a 70h command.
PDF: 09005aef814b01a2 / Source: 09005aef814b01c7 2_4_8gb_nand_m49a__2.fm - Rev. A 3/06 EN
30
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved.
2Gb, 4GB, 8Gb: x8, x16 NAND Flash Memory Command Definitions Internal Data Move
An internal data move requires two command sequences. Issue a READ for INTERNAL DATA MOVE (00h-35h) command first, then the PROGRAM for INTERNAL DATA MOVE (85h-10h) command. Data moves are only supported within the die from which data is read. READ FOR INTERNAL DATA MOVE 00h-35h The READ for INTERNAL DATA MOVE (00h-35h)command is used in conjunction with the PROGRAM for INTERNAL DATA MOVE (85h-10h) command. First (00h) is written to the command register, then the internal source address is written (five cycles). After the address is input, the READ for INTERNAL DATA MOVE (35h) command writes to the command register. This transfers a page from memory into the cache register. The written column addresses are ignored even though all five ADDRESS cycles are required. The memory device is now ready to accept the PROGRAM for INTERNAL DATA MOVE command. Refer to the command description in the following section for details. PROGRAM for INTERNAL DATA MOVE 85h-10h After the READ for INTERNAL DATA MOVE (00h-35h) command has been issued and R/B# goes HIGH, the PROGRAM for INTERNAL DATA MOVE (85h-10h) command can be written to the command register. This command transfers the data from the cache register to the data register and programming of the new destination page begins. The sequence: 85h, destination address (five cycles), then 10h, is written to the device. After 10h is written, R/B# goes LOW while the control logic automatically programs the new page. The READ STATUS command can be used instead of the R/B# line to determine when the write is complete. When status register bit 6 = "1," bit 0 indicates if the operation was successful. The RANDOM DATA INPUT (85h) command can be used during the PROGRAM for INTERNAL DATA MOVE command sequence to modify a word or multiple words of the original data. First, data is copied into the cache register using the 00h-35h command sequence, then the RANDOM DATA INPUT (85h) command is written along with the address of the data to be modified next. New data is input on the external data pins. This copies the new data into the cache register.
www..net
When 10h is written to the command register, the original data plus the modified data are transferred to the data register, and programming of the new page is started. The RANDOM DATA INPUT command can be issued as many times as necessary before starting the programming sequence with 10h (see Figures 25 and 26 on page 32). Because INTERNAL DATA MOVE operations do not use external memory, ECC cannot be used to check for errors before programming the data to a new page. This can lead to a data error if the source page contains a bit error due to charge loss or charge gain. In the case that multiple INTERNAL DATA MOVE operations are performed, these bit errors may accumulate without correction. For this reason, it is highly recommended that systems using INTERNAL DATA MOVE operations also use a robust ECC scheme that can correct two or more bits per sector.
PDF: 09005aef814b01a2 / Source: 09005aef814b01c7 2_4_8gb_nand_m49a__2.fm - Rev. A 3/06 EN
31
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved.
2Gb, 4GB, 8Gb: x8, x16 NAND Flash Memory Command Definitions
Figure 25: INTERNAL DATA MOVE
tR tPROG
R/B#
I/Ox
00h
Address (5 Cycles)
35h
85h
Address (5 Cycles)
10h
70h
Status
Figure 26:
INTERNAL DATA MOVE with RANDOM DATA INPUT
tR tPROG
R/B#
Address (5 Cycles) Address (5 Cycles) Address (2 Cycles)
I/Ox
00h
35h
85h
Data
85h
Data 10h
70h
Status
Unlimited number of repetitions.
www..net
PDF: 09005aef814b01a2 / Source: 09005aef814b01c7 2_4_8gb_nand_m49a__2.fm - Rev. A 3/06 EN
32
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved.
2Gb, 4GB, 8Gb: x8, x16 NAND Flash Memory Command Definitions BLOCK ERASE Operation
BLOCK ERASE 60h-D0h Erasing occurs at the block level. For example, the MT29F2G08xxC device has 2,048 erase blocks organized into 64 pages per block, 2,112 bytes per page (2,048 + 64 bytes). Each block is 132K bytes (128K + 4K bytes). The BLOCK ERASE command operates on one block at a time (see Figure 27). Three cycles of addresses BA[17:6] and PA[5:0] are required. Although page addresses PA[5:0] are loaded, they are "Don't Care" and are ignored for BLOCK ERASE operations. See Table 4 on page 13 for addressing details. The actual command sequence is a two-step process. The ERASE SETUP (60h) command is first written to the command register. Then three cycles of addresses are written to the device. Next, the ERASE CONFIRM (D0h) command is written to the command register. At the rising edge of WE#, R/B# goes LOW and the control logic automatically controls the timing and erase-verify operations. R/B# stays LOW for the entire tBERS erase time. The READ STATUS (70h) command can be used to check the status of the BLOCK ERASE operation. When bit 6 = "1" the ERASE operation is complete. Bit 0 indicates a pass/fail condition where "0" = pass (see Figure 27, and Table 11 on page 28). Figure 27:
CLE
BLOCK ERASE Operation
CE#
WE#
ALE tBERS
www..net
R/B#
RE#
I/Ox
60h
Address Input (3 Cycles)
D0h
70h
Status
I/O 0 = 0 ERASE successful I/O 0 = 1 ERASE error
Don't Care
PDF: 09005aef814b01a2 / Source: 09005aef814b01c7 2_4_8gb_nand_m49a__2.fm - Rev. A 3/06 EN
33
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved.
2Gb, 4GB, 8Gb: x8, x16 NAND Flash Memory Command Definitions One Time Programmable (OTP) Area
This Micron NAND Flash device offers a protected, one-time programmable NAND Flash memory area. Ten full pages (2,112 bytes or 1,056 words per page) of OTP data is available on the device, and the entire range is guaranteed to be good from the factory. The OTP area is accessible only through the OTP commands. Customers can use the OTP area any way they desire; typical uses include programming serial numbers or other data for permanent storage. In Micron NAND Flash devices, the OTP area leaves the factory in a non-written state (all bits are "1s"). Programming or partial-page programming enables the user to program only "0" bits in the OTP area. The OTP area cannot be erased, even if it is not protected. Protecting the OTP area simply prevents further programming of the OTP area. While the OTP area is referred to as "one-time programmable," Micron provides a unique way to program and verify data--before permanently protecting it and preventing future changes. OTP programming and protection are accomplished in two discrete operations. First, using the OTP DATA PROGRAM (A0h-10h) command, an OTP page is programmed entirely in one operation, or in up to four partial-page programming sequences. Second, the OTP area is permanently protected from further programming using the OTP DATA PROTECT (A5h-10h) command. The pages within the OTP area can always be read using the OTP DATA READ (AFh-30h) command, whether or not it is protected. OTP DATA PROGRAM A0h-10h The OTP DATA PROGRAM (A0h-10h) command is used to write data to the pages within the OTP area. An entire page can be programmed at one time, or the page can be partially programmed up to four times. There is no ERASE operation for the OTP pages. The OTP DATA PROGRAM enables programming into an offset of an OTP page, using the two bytes of column address (CA[11:0]). The command is not compatible with the RANDOM DATA INPUT (85h) command. The OTP DATA PROGRAM command will not execute if the OTP area has been protected. To use the OTP DATA PROGRAM command, issue the A0h command. Then issue five ADDRESS cycles: the first two ADDRESS cycles are the column address, and for the remaining three cycles, select a page in the range of 02h-00h-00h through 0Bh-00h-00h. Next, write the data: from 1 to 2,112 bytes (x8 device), or from 1 to 1,056 words (x16 device). After data input is complete, issue the 10h command. The internal control logic automatically executes the proper programming algorithm and controls the necessary timing for programming and verification. Program verification only detects "1s" that are not successfully written to "0s." R/B# goes LOW during the duration of the array programming time (tPROG). The READ STATUS (70h) command is the only command valid during the OTP DATA PROGRAM operation. Bit 5 of the status register will reflect the state of R/B#. If bit 7 is "0," the OTP area has been protected; otherwise, it is not protected. When the device is ready, read bit 0 of the status register to determine if the operation passed or failed (see Table 11 on page 28). It is possible to program each OTP page a maximum of four times.
www..net
PDF: 09005aef814b01a2 / Source: 09005aef814b01c7 2_4_8gb_nand_m49a__2.fm - Rev. A 3/06 EN
34
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved.
2Gb, 4GB, 8Gb: x8, x16 NAND Flash Memory Command Definitions
Figure 28:
CLE
OTP DATA PROGRAM
CE# tWC WE# tWB ALE tPROG
RE#
I/Ox
A0h OTP DATA INPUT Command
Col Add 1
Col Add 2
OTP Page1
00h
00h
DIN N
DIN M
10h PROGRAM Command
70h READ STATUS Command
Status
1 up to m bytes Serial Input
R/B# x8 device: m = 2,112 bytes x16 device: m = 1,056 words OTP data written (following "good" status confirmation)
Don't Care
Notes: 1. The OTP page must be within the 02h-0Bh range.
www..net
PDF: 09005aef814b01a2 / Source: 09005aef814b01c7 2_4_8gb_nand_m49a__2.fm - Rev. A 3/06 EN
35
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved.
2Gb, 4GB, 8Gb: x8, x16 NAND Flash Memory Command Definitions
OTP DATA PROTECT A5h-10h The OTP DATA PROTECT (A5h-10h) command is used to protect the data in the OTP area. After the data is protected it cannot be programmed further. When the OTP area is protected, the pages within the area are no longer programmable and cannot be unprotected. To use the OTP DATA PROTECT command, issue the A5h command. Next, issue the following five address cycles: 00h-00h-01h-00h-00h. Finally, issue the 10h command. R/B# goes LOW while the OTP area is being protected. The protect command duration is similar to a normal page programming operation, tPROG. The READ STATUS (70h) command is the only command valid during the OTP DATA PROTECT operation. Bit 5 of the status register will reflect the state of R/B#. When the device is ready, read bit 0 of the status register to determine if the operation passed or failed (see Table 11 on page 28). Figure 29:
CLE
OTP DATA PROTECT
CE# tWC WE# tWB ALE tPROG
RE#
I/Ox
A5h OTP DATA PROTECT Command
Col 00h
Col 00h
01h
00h
00h
10h PROGRAM Command
70h READ STATUS Command
Status
www..net
R/B# OTP data protected1
Don't Care
Notes: 1. OTP data is protected following "good" status confirmation.
PDF: 09005aef814b01a2 / Source: 09005aef814b01c7 2_4_8gb_nand_m49a__2.fm - Rev. A 3/06 EN
36
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved.
2Gb, 4GB, 8Gb: x8, x16 NAND Flash Memory Command Definitions
OTP DATA READ AFh-30h The OTP DATA READ (AFh-30h) command is used to read data from a page within the OTP area. An OTP page within the OTP area is available for reading data whether or not the area is protected. To use the OTP DATA READ command, issue the AFh command. Then issue five ADDRESS cycles: the first two ADDRESS cycles are the column address, and for the remaining three cycles select a page in the range of 02h-00h-00h through 0Bh-00h-00h. Finally, issue the 30h command. R/B# goes LOW (tR) while the data is moved from the OTP page to the data register. The READ STATUS (70h) command and the RESET (FFh) command are the only commands valid during the OTP DATA READ operation. Bit 5 of the status register will reflect the state of R/B#. For details, refer to Table 11 on page 28. Normal READ operation timings apply to OTP read accesses (see Figure 30). Additional pages within the OTP area can be selected by repeating the OTP DATA READ command. Figure 30:
CLE
OTP DATA READ
CE#
WE#
ALE tR RE#
www..net
I/Ox
AFh
Col Add 1
Col Add 2
OTP Page1
00h
00h
30h
DOUT N Busy
DOUT N+1
DOUT M
R/B# Don't Care
Notes: 1. The OTP page must be within the 02h-0Bh range.
PDF: 09005aef814b01a2 / Source: 09005aef814b01c7 2_4_8gb_nand_m49a__2.fm - Rev. A 3/06 EN
37
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved.
2Gb, 4GB, 8Gb: x8, x16 NAND Flash Memory Command Definitions RESET Operation
RESET FFh The RESET command is used to put the memory device into a known condition and to abort a command sequence in progress. READ, PROGRAM, and ERASE commands can be aborted while the device is in the busy state. The contents of the memory location being programmed or the block being erased are no longer valid. The data may be partially erased or programmed, and is invalid. The command register is cleared and is ready for the next command. The data register and cache register contents are invalid. The status register contains the value E0h when WP# is HIGH; otherwise it is written with a 60h value. R/B# goes low for tRST after the RESET command is written to the command register (see Figure 31 and Table 12). Figure 31:
CLE
RESET Operation
CE# tWB WE# tRST R/B#
I/Ox
FF RESET Command
www..net
Table 12:
Condition WP# HIGH WP# LOW
Status Register Contents After RESET Operation
Status Ready Ready and write protected Bit 7 1 0 Bit 6 1 1 Bit 5 1 1 Bit 4 0 0 Bit 3 0 0 Bit 2 0 0 Bit 1 0 0 Bit 0 0 0 Hex E0h 60h
PDF: 09005aef814b01a2 / Source: 09005aef814b01c7 2_4_8gb_nand_m49a__2.fm - Rev. A 3/06 EN
38
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved.
2Gb, 4GB, 8Gb: x8, x16 NAND Flash Memory Command Definitions WRITE PROTECT Operation
It is possible to enable and disable PROGRAM and ERASE commands using the WP# pin. The following figures illustrate the setup time (tWW) required from WP# toggling until a PROGRAM or ERASE command is latched into the command register. After command cycle 1 is latched, WP# must not be toggled until the command is complete and the device is ready (status register bit 5 is "1"). Figure 32: ERASE Enable
WE# tWW I/Ox 60h D0h
WP#
R/B#
Figure 33:
ERASE Disable
WE# tWW I/Ox 60h D0h
WP#
R/B#
www..net
Figure 34:
PROGRAM Enable
WE# tWW I/Ox 80h 10h
WP#
R/B#
PDF: 09005aef814b01a2 / Source: 09005aef814b01c7 2_4_8gb_nand_m49a__2.fm - Rev. A 3/06 EN
39
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved.
2Gb, 4GB, 8Gb: x8, x16 NAND Flash Memory Error Management
Figure 35: PROGRAM Disable
WE# tWW I/Ox 80h 10h
WP#
R/B#
Error Management
Micron NAND Flash devices are specified to have a minimum of 2,008 (NVB) valid blocks out of every 2,048 total available blocks. This means the devices may have blocks that are invalid when they are shipped. An invalid block is one that contains one or more bad bits. Additional bad blocks may develop with use. However, the total number of available blocks will not fall below NVB during the endurance life of the product. Although NAND Flash memory devices may contain bad blocks, they can be used quite reliably in systems that provide bad-block mapping, bad-block replacement, and error correction algorithms. This type of software environment ensures data integrity. Internal circuitry isolates each block from other blocks, so the presence of a bad block does not affect the operation of the rest of the Flash device. The first block (physical block address 00h) for each CE#is guaranteed to be free of defects (up to 1,000 PROGRAM/ERASE cycles) when shipped from the factory. This provides a reliable location for storing boot code and critical boot information. Before NAND Flash devices are shipped from Micron, they are erased. The factory identifies invalid blocks before shipping by programming data other than FFh (x8) or FFFFh (x16) into the first spare location (column address 2,048 for x8 devices, or column address 1,024 for x16 devices) of the first or second page of each bad block. System software should check the first spare address on the first two pages of each block prior to performing any erase or programming operations on the NAND Flash device. A bad block table can then be created, allowing system software to map around these areas. Factory testing is performed under worst-case conditions. Because blocks marked "bad" may be marginal, it may not be possible to recover this information if the block is erased. Over time, some memory locations may fail to program or erase properly. In order to ensure that data is stored properly over the life of the NAND Flash device, certain precautions must be taken, such as: * Always check status after a PROGRAM, ERASE, or DATA MOVE operation. * Use some type of error detection and correction algorithm to recover from single-bit errors per 528 bytes of data. * Use a bad-block replacement algorithm.
www..net
PDF: 09005aef814b01a2 / Source: 09005aef814b01c7 2_4_8gb_nand_m49a__2.fm - Rev. A 3/06 EN
40
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved.
2Gb, 4GB, 8Gb: x8, x16 NAND Flash Memory Electrical Characteristics
Electrical Characteristics
Stresses greater than those listed under "Absolute Maximum Ratings" (see Table 13) may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not guaranteed. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Table 13: Absolute Maximum Ratings by Device
Voltage on any pin relative to VSS Parameter/Condition Voltage input VCC supply voltage Storage temperature Short circuit output current, I/Os MT29FxGxxxAC MT29FxGxxxBC MT29FxGxxxAC MT29FxGxxxBC Symbol VIN VCC TSTG Min -0.6 -0.6 -0.6 -0.6 -65 - Max +4.6 +2.4 +4.6 +2.4 +150 5 Unit V V V V C mA
Table 14:
Recommended Operating Conditions
Symbol Commercial Extended MT29FxGxxxAC MT29FxGxxxBC TA Vcc Vss Min 0 -40 2.7 1.70 0 Typ - - 3.3 1.8 0 Max +70 +85 3.6 1.95 0 Unit
oC oC
Parameter/Condition Operating temperature VCC supply voltage Ground supply voltage
V V V
VCC Power Cycling
Micron NAND Flash devices are designed to prevent data corruption during power transitions. VCC is internally monitored. When VCC goes below approximately 1.1V (1.8V device), or 2.0V (3V device), PROGRAM and ERASE functions are disabled. WP# provides additional hardware protection. WP# should be kept at VIL during power cycling. When VCC reaches approximately 1.5V (1.8V device) or 2.5V (3V device), a minimum of 10s should be allowed for the NAND Flash to initialize before executing any commands (see Figure 36). AC Waveforms During Power Transitions
3V device: 2.5V 1.8V device: 1.5V Vcc HIGH WP# 3V device: 2.5V 1.8V device: 1.5V
www..net
Figure 36:
WE#
10s
R/B# Don't Care
PDF: 09005aef814b01a2 / Source: 09005aef814b01c7 2_4_8gb_nand_m49a__2.fm - Rev. A 3/06 EN
Undefined
41
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved.
2Gb, 4GB, 8Gb: x8, x16 NAND Flash Memory Electrical Characteristics
Table 15:
Parameter Sequential read current Program current Erase current Standby current (TTL) Standby current (CMOS) MT29F2GxxAAC MT29F4GxxBAC MT29F8GxxFAC Input leakage current MT29F2GxxAAC MT29F4GxxBAC MT29F8GxxFAC Input leakage current (PRE) Output leakage current MT29F2GxxAAC MT29F4GxxBAC MT29F8GxxFAC Input high voltage Input low voltage (all inputs) Output high voltage Output low voltage Output low current (R/B#) Note:
t
M29FxGxxxAC 3V Device DC and Operating Characteristics
Conditions RC = 30ns, CE# = VIL, IOUT = 0mA - - CE# = VIH, PRE = WP# = 0V/VCC CE# = VCC - 0.2V, PRE = WP# = 0V/VCC Symbol Icc1 ICC2 ICC3 ISB1 Min - - - - Typ 15 15 15 - Max 30 30 30 1 Unit mA mA mA mA
ISB2
- - - - - - -
10 20 40 - - - -
50 100 200 10 20 40 10
A A A A A A A
VIN = 0V to VCC
ILI
VIN = 0V/VCC
ILIPRE
VOUT = 0V to VCC
ILO
I/O[7:0], I/O[15:0] CE#, CLE, ALE, WE#, RE#, WP#, PRE, R/B# - IOH = -400A IOL = 2.1mA VOL = 0.4V
VIH VIL VOH VOL IOL (R/B#)
- - - 0.8 x VCC -0.3 2.4 - 8
- - - - - - - 10
10 20 40 VCC + 0.3 0.2 x VCC - 0.4 -
A A A V V V V mA
The PRE function is available only on commercial-temperature devices.
www..net
PDF: 09005aef814b01a2 / Source: 09005aef814b01c7 2_4_8gb_nand_m49a__2.fm - Rev. A 3/06 EN
42
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved.
2Gb, 4GB, 8Gb: x8, x16 NAND Flash Memory Electrical Characteristics
Table 16:
Parameter Sequential read current Program current Erase current Standby current (TTL) Standby current (CMOS) MT29F2GxxAAC MT29F4GxxBAC MT29F8GxxFAC Input leakage current MT29F2GxxAAC MT29F4GxxBAC MT29F8GxxFAC Output leakage current MT29F2GxxAAC MT29F4GxxBAC MT29F8GxxFAC Input high voltage Input low voltage (all inputs) Output high voltage Output low voltage Output low current Note:
t
M29FxGxxxBC 1.8V Device DC and Operating Characteristics
Conditions RC = 50ns, CE# = VIL, IOUT = 0mA - - CE# = VIH, PRE = WP# = 0V/VCC CE# = VCC - 0.2V, PRE = WP# = 0V/VCC Symbol Icc1 ICC2 ICC3 ISB1 Min - - - - Typ 8 8 8 - Max 15 15 15 1 Unit mA mA mA mA
ISB2
- - - - - - - - - 0.8 x VCC -0.3
10 20 40 - - - - - - - - - - 4
50 100 200 10 20 40 10 20 40 VCC + 0.3 0.2 x VCC - 0.1 -
A A A A A A A A A V V V V mA
VIN = 0V to VCC
ILI
VOUT = 0V to VCC
ILO
I/O [7:0], I/O [15:0] CE#, CLE, ALE, WE#, RE#, WP#, PRE, R/B# - IOH = -100A IOL = 100A VOL = 0.1V
VIH VIL
VOH VCC - 0.1 VOL - IOL (R/B#) 3
The PRE function is not available on 1.8V devices.
Table 17:
Parameter
Valid Blocks
Symbol NVB Device MT29F2GxxAxC MT29F4GxxBxC MT29F8GxxFxC Min 2,008 4,016 8,032 Max 2,048 4,096 8,192 Unit Blocks Notes 1, 2 3
Valid block number
www..net
Notes: 1. Invalid blocks are blocks that contain one or more bad bits. The device may contain bad blocks upon shipment. Additional bad blocks may develop over time; however, the total number of available blocks will not drop below NVB during the endurance life of the device. Do not erase or program blocks marked invalid by the factory. 2. Block 00h (the first block) is guaranteed to be valid and does not require error correction up to 1K PROGRAM/ERASE cycles. 3. The number of invalid blocks in each 4Gb section will not exceed 80.
PDF: 09005aef814b01a2 / Source: 09005aef814b01c7 2_4_8gb_nand_m49a__2.fm - Rev. A 3/06 EN
43
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved.
2Gb, 4GB, 8Gb: x8, x16 NAND Flash Memory Electrical Characteristics
Table 18:
Description Input capacitance
Capacitance
Symbol CIN Device MT29F2GxxAxC MT29F4GxxBxC MT29F8GxxFxC MT29F2GxxAxC MT29F4GxxBxC MT29F8GxxFxC Max 10 20 40 10 20 40 Unit pF Notes 1, 2
Input/output capacitance (I/O)
CIO
pF
1, 2
Notes: 1. These parameters are verified in device characterization and are not 100 percent tested. 2. Test conditions: Tc = 25C; f = 1 MHz; VIN = 0V.
Table 19:
Parameter
Test Conditions
Value MT29FxGxxxAC MT29FxGxxxBC 0.0V to VCC (2.7V-3.6V) 0.0V to VCC (1.70V-1.95V) 5ns VCC/2 1 TTL GATE and CL = 50pF 1 TTL GATE and CL = 100pF 1 TTL GATE and CL = 30pF Notes
Input pulse levels
Input rise and fall times Input and output timing levels Output load MT29FxGxxxAC (VCC = 3.0V 10%) MT29FxGxxxAC (VCC = 3.3V 10%) MT29FxGxxxBC (Vcc = 1.70-1.95V)
1 1 1
Notes: 1. Verified in device characterization; not 100 percent tested.
Table 20:
AC Characteristics: Command, Data, and Address Input
3V x16 and 1.8V 3V x8 Min 100 5 10 5 5 10 15 5 10 30 10 15 30 Max - - - - - - - - - - - - - Unit ns ns ns ns ns ns ns ns ns ns ns ns ns Notes 1 2 2 2 2 2 2 2 2 2, 3 2 2
Parameter ALE to data start ALE hold time ALE setup time CE# hold time CLE hold time CLE setup time CE# setup time Data hold time Data setup time Write cycle time WE# pulse width HIGH WE# pulse width WP# setup time
www..net
Symbol
tADL tALH tALS tCH tCLH t t
Min 100 10 25 10 10 25 35 10 20 45 15 25 30
Max - - - - - - - - - - - - -
CLS CS tDH tDS tWC t WH t WP tWW
Notes: 1. Timing for tADL begins in the ADDRESS cycle, on the final rising edge of WE#, and ends with the first rising edge of WE# for data input. 2. For PAGE READ CACHE MODE and PROGRAM PAGE CACHE MODE operations, the 3V x16 AC characteristics apply for 3V x8 devices. 3. For 1.8V devices: During PROGRAM PAGE CACHE MODE and PAGE READ CACHE MODE operations, when VCC = 1.70V, tWC = 55ns MIN.
PDF: 09005aef814b01a2 / Source: 09005aef814b01c7 2_4_8gb_nand_m49a__2.fm - Rev. A 3/06 EN
44
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved.
2Gb, 4GB, 8Gb: x8, x16 NAND Flash Memory Electrical Characteristics
Table 21: AC Characteristics: Normal Operation
3V x16 and 1.8V Parameter ALE to RE# delay CE# access time CE# HIGH to output High-Z CLE to RE# delay Cache busy in page read cache mode (first 31h) Cache busy in page read cache mode (next 31h and 3Fh) Output High-Z to RE# LOW Data output hold time Data transfer from NAND Flash array to data register READ cycle time RE# access time RE# HIGH hold time RE# HIGH to output High-Z RE# pulse width Data transfer from NAND Flash array to data register at powerup with PRE enabled at 3.3V Vcc Ready to RE# LOW Reset time (READ/PROGRAM/ERASE) WE# HIGH to busy WE# HIGH to RE# LOW Symbol
tAR t t
3V x8 Min 10 - - 10 -
t
Min 10 - - 10 -
t
Max - 45 20 - 3 25 - - 25 - 30 - 30 - 25
Max 23 20 - 3 25 - - 25 - 18 - 30 - 25
Unit ns ns ns ns s s ns ns s ns ns ns ns ns s
Notes 1 2
CEA CHZ tCLR t DCBSYR1
t
DCBSYR2
DCBSYR1 0 15 - 50 - 15 - 25 -
DCBSYR1 0 15 - 30 - 10 - 15 -
tIR tOH tR tRC tREA tREH tRHZ tRP tRPRE
1
1 1 1 2 1 3
tRR tRST tWB tWHR
20 - - 60
- 5/10/500 100 -
20 - - 60
- 5/10/500 100 -
ns s ns ns
4 4, 5
www..net
Notes: 1. For PAGE READ CACHE MODE and PROGRAM PAGE CACHE MODE operations, the 3V x16 AC characteristics apply for 3V x8 devices. 2. Transition is measured 200mV from steady-state voltage with load. This parameter is sampled and not 100 percent tested. 3. The PRE function is available only on 3V commercial-temperature devices. 4. If RESET (FFh) command is loaded at ready state, the device goes busy for maximum 5s. 5. Do not issue a new command during tWB, even if R/B# is ready.
Table 22:
Parameter NOP t BERS t CBSY tLPROG tPROG
PROGRAM/ERASE Characteristics
Description Number of partial page programs Block erase time Busy time for cache program Last page program time Page program time Notes: 1. 2. 3. Typ - 2 3 - 300 Max 8 3 700 - 700 Unit Cycles ms s - s Notes 1 2 3
Eight cycles total to the same page. MAX time depends on timing between internal program completion and data in. tLPROG = tPROG (last page) + tPROG (last - 1 page) - command load time (last page) - address load time (last page) - data load time (last page).
tCBSY
PDF: 09005aef814b01a2 / Source: 09005aef814b01c7 2_4_8gb_nand_m49a__2.fm - Rev. A 3/06 EN
45
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved.
2Gb, 4GB, 8Gb: x8, x16 NAND Flash Memory Timing Diagrams
Timing Diagrams
Figure 37: COMMAND LATCH Cycle
CLE
tCLS tCS tCLH tCH
CE#
tWP
WE#
tALS tALH
ALE
tDS tDH
I/Ox
Command
Don't Care
Note:
x16: I/O[15:8] must be set to "0."
Figure 38:
ADDRESS LATCH Cycle
CLE
tCLS tCS
www..net
tWC
CE#
tWP
WE#
tWH
tALS tALH
ALE
tDS tDH
I/Ox Col Add 1 Col Add 2 Row Add 1 Row Add 2 Row Add 3
Don't Care
Undefined
Note:
x16: I/O [15:8] must be set to "0."
PDF: 09005aef814b01a2 / Source: 09005aef814b01c7 2_4_8gb_nand_m49a__2.fm - Rev. A 3/06 EN
46
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved.
2Gb, 4GB, 8Gb: x8, x16 NAND Flash Memory Timing Diagrams
Figure 39: INPUT DATA LATCH Cycle
CLE tCLH
CE# tALS tCH
ALE tWC tWP WE# tWH tDS tDH I/Ox
DIN 0
tWP
tWP
tDS tDH
DIN 1
tDS tDH
DIN Final1
Don't Care
Notes: 1. DIN Final = 2,111 (x8) or 1,055 (x16).
Figure 40:
SERIAL ACCESS Cycle After READ
tCEA
CE# tREA
www..net
tREA tRP tREH
tREA tOH
tCHZ
RE# tRHZ tRHZ tOH I/Ox tRR R/B# Don't Care DOUT tRC DOUT DOUT
PDF: 09005aef814b01a2 / Source: 09005aef814b01c7 2_4_8gb_nand_m49a__2.fm - Rev. A 3/06 EN
47
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved.
2Gb, 4GB, 8Gb: x8, x16 NAND Flash Memory Timing Diagrams
Figure 41: READ STATUS Cycle
tCLR CLE tCLS tCLH
tCS CE# tWP WE# tCEA tWHR RE# tRP tCH
tCHZ tOH
tRHZ tDS tDH tIR tOH tREA Status Output
I/Ox
70h
Don't Care
Figure 42:
CLE
PAGE READ
tCLR
CE#
www..net
tWC
WE#
tWB tAR
ALE
tR tRC tRHZ
RE#
tRR tRP DOUT N DOUT N+1 DOUT M
I/Ox
00h
Col Add 1
Col Add 2
Row Add 1
Row Add 2
Row Add 3
30h
Busy
R/B# Don't Care
PDF: 09005aef814b01a2 / Source: 09005aef814b01c7 2_4_8gb_nand_m49a__2.fm - Rev. A 3/06 EN
48
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved.
2Gb, 4GB, 8Gb: x8, x16 NAND Flash Memory Timing Diagrams
Figure 43:
CLE
PAGE READ Operation with CE# "Don't Care"
CE#
RE#
ALE tR R/B#
WE#
I/Ox
00h
Address (5 Cycles)
30h
Data Output
tCEA
CE#
tREA
RE#
Don't Care
Out
I/Ox
Figure 44:
CLE
RANDOM DATA READ
tCLR CE#
www..net
WE# tWB ALE tR RE# tRR I/Ox 00h
Col Add 1 Col Add 2 Row Add1 Row Add 2 Row Add 3
tAR
tWHR
tRC
tREA
30h
DOUT
N
DOUT
N+1
05h
Col Add 1
Col Add 2
E0h
DOUT
M
DOUT
M+1
Column Address N
Column Address M
Busy R/B#
Don't Care
PDF: 09005aef814b01a2 / Source: 09005aef814b01c7 2_4_8gb_nand_m49a__2.fm - Rev. A 3/06 EN
49
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved.
Figure 45:
PAGE READ CACHE MODE Timing Diagram, Part 1 of 2
www..net
PDF: 09005aef814b01a2 / Source: 09005aef814b01c7 2_4_8gb_nand_m49a__2.fm - Rev. A 3/06 EN
CLE
tCLS tCLH
tCS
CE#
tCH
tWC
WE#
tCEA
ALE
tRC
RE#
tR tDS tDH tWB tRR
Col Add 1 Col Add 2 Row Add 1 Row Add 2 Row Add 3
30h 31h DOUT 0 DOUT 1 DOUT 31h DOUT 0
tREA
I/Ox
00h
Column Address 00h
Page Address M
tDCBSYR1
Page Address M
tDCBSYR2
Page Address M+1
50
R/B#
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved.
2Gb, 4GB, 8Gb: x8, x16 NAND Flash Memory Timing Diagrams
Column Address 0
Column Address 0
1
Continued to 1 of next page
Don't Care
Figure 46:
PAGE READ CACHE MODE Timing Diagram, Part 2 of 2
www..net
PDF: 09005aef814b01a2 / Source: 09005aef814b01c7 2_4_8gb_nand_m49a__2.fm - Rev. A 3/06 EN
CLE
tCLS tCLH
tCS
tCH
CE#
WE#
tCEA
ALE
tRC
RE#
tWB tDS tDH
tRR
tREA
DOUT 0
I/Ox
31h
DOUT 1
31h
DOUT 0
DOUT 1
3Fh
DOUT 0
DOUT 1
tDCBSYR2
Page Address M+1
tDCBSYR2
Page Address M+2
tDCBSYR2
Page Address M+x
51
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved.
2Gb, 4GB, 8Gb: x8, x16 NAND Flash Memory Timing Diagrams
R/B#
Column Address 0 Column Address 0 Column Address 0
1
Continued from 1 of previous page
Don't Care
Figure 47:
PAGE READ CACHE MODE Timing without R/B#, Part 1 of 2
www..net
PDF: 09005aef814b01a2 / Source: 09005aef814b01c7 2_4_8gb_nand_m49a__2.fm - Rev. A 3/06 EN
CLE
tCLS tCLH
tCS CE#
tCH
tWC WE# tCEA ALE tRC RE# tDS tDH I/Ox
00h
tREA
Col Add 1 Col Add 2 Row Add 1 Row Add 2 Row Add 3
30h 70h Status 31h 70h Status 00h DOUT 0 DOUT 1 DOUT 31h 70h Status 00h DOUT 0
Column Address 00h
Page Address M
I/O 5 = 0, Busy = 1, Ready
I/O 6 = 0, Cache Busy = 1, Cache Ready
Page Address M
I/O 6 = 0, Cache Busy = 1, Cache Ready
Page Address M+1
52
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved.
2Gb, 4GB, 8Gb: x8, x16 NAND Flash Memory Timing Diagrams
Column Address 0
Column Address 0
1
Continued to 1 of next page
Don't Care
Figure 48:
PAGE READ CACHE MODE Timing without R/B#, Part 2 of 2
www..net
PDF: 09005aef814b01a2 / Source: 09005aef814b01c7 2_4_8gb_nand_m49a__2.fm - Rev. A 3/06 EN
CLE
tCLS
tCLH
tCS
CE#
tCH
WE#
tCEA
ALE
tRC
RE#
tDS tDH
I/Ox
DOUT 31h 70h Status
tREA
00h
DOUT 0
DOUT 1 Page Address M+1
DOUT
31h
70h
Status
00h
DOUT 0
DOUT 1 Page Address M+2
DOUT
3Fh
70h
Status
00h
DOUT 0
DOUT 1 Page Address M+x
DOUT
I/O 6 = 0, Cache Busy = 1, Cache Ready Column Address 0
I/O 6 = 0, Cache Busy = 1, Cache Ready
I/O 6 = 0, Cache Busy = 1, Cache Ready
53
1
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved.
2Gb, 4GB, 8Gb: x8, x16 NAND Flash Memory Timing Diagrams
Column Address 0
Column Address 0
Don't Care
Continued from 1 of previous page
2Gb, 4GB, 8Gb: x8, x16 NAND Flash Memory Timing Diagrams
Figure 49:
CLE
READ ID Operation
CE#
WE#
tAR
ALE
RE#
tWHR tREA Byte 0 Byte 1 Byte 2 Byte 3
I/Ox
90h
00h Address, 1 Cycle
Note:
See Table 10 on page 27 for byte definitions.
Figure 50:
CLE
PROGRAM PAGE Operation
CE#
tWC tADL
WE#
www..net
tWB
tPROG
ALE
RE#
I/Ox
80h SERIAL DATA INPUT Command
Col Add 1
Col Add 2
Row Add 1
Row Add 2
Row Add 3
DIN N
DIN M
10h PROGRAM Command
70h READ STATUS Command
Status
1 up to m bytes Serial Input
R/B#
x8 device: m = 2,112 byte x16 device: m = 1,056 byte
Don't Care
PDF: 09005aef814b01a2 / Source: 09005aef814b01c7 2_4_8gb_nand_m49a__2.fm - Rev. A 3/06 EN
54
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved.
2Gb, 4GB, 8Gb: x8, x16 NAND Flash Memory Timing Diagrams
Figure 51:
CLE
PROGRAM PAGE Operation with CE# "Don't Care"
CE#
WE#
ALE
I/Ox
80h
Address (5 Cycles)
Data
Input
Data
Input
10h
tCS
CE#
tCH
tWP
WE#
Don't Care
Figure 52:
CLE
PROGRAM PAGE Operation with RANDOM DATA INPUT
CE#
tWC tADL tADL
WE# www..net
tWB tPROG
ALE
RE# I/Ox
80h
Col Add 1 Col Add 2 Row Add 1 Row Add 2 Row Add 3 DIN N DIN N+1
85h
RANDOM DATA INPUT Command
Col Add 1
Col Add 2
DIN N Serial Input
DIN N+1
10h
PROGRAM Command
70h
READ STATUS Command
Status
SERIAL DATA INPUT Command
Serial Input
Column Address
R/B# Don't Care
PDF: 09005aef814b01a2 / Source: 09005aef814b01c7 2_4_8gb_nand_m49a__2.fm - Rev. A 3/06 EN
55
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved.
2Gb, 4GB, 8Gb: x8, x16 NAND Flash Memory Timing Diagrams
Figure 53:
CLE
INTERNAL DATA MOVE
CE#
tWC tADL
WE#
tWB tWB tPROG tWHR
ALE
RE# I/Ox
00h Col Col Row Row Row Add 1 Add 2 Add 1 Add 2 Add 3 35h
tR 85h Col Col Row Row Row Add 1 Add 2 Add 1 Add 2 Add 3
Data 1 Data N
10h Busy
70h
READ STATUS Command
Status
Busy
R/B#
INTERNAL DATA MOVE
Don't Care
Figure 54:
CLE
PROGRAM PAGE CACHE MODE
CE#
tWC tADL
WE#
tWBtCBSY tWB tLPROG tWHR
ALE
www..net RE#
I/Ox
80h
Col Col Row Row Row Add 1 Add 2 Add 1 Add 2 Add 3
SERIAL DATA INPUT
DIN DIN 15h N M Serial Input PROGRAM
80h
Col Col Row Row Row Add 1 Add 2 Add 1 Add 2 Add 3
DIN N
DIN M
10h PROGRAM
70h
Status
R/B#
Last Page - 1 Last Page
Don't Care
PDF: 09005aef814b01a2 / Source: 09005aef814b01c7 2_4_8gb_nand_m49a__2.fm - Rev. A 3/06 EN
56
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved.
Figure 55:
PROGRAM PAGE CACHE MODE Ending on 15h
www..net
PDF: 09005aef814b01a2 / Source: 09005aef814b01c7 2_4_8gb_nand_m49a__2.fm - Rev. A 3/06 EN
CLE
CE# tWC WE# tWHR ALE tWHR tADL tADL
RE# I/Ox
80h
SERIAL DATA INPUT
Col Add 1
Col Add 2
Row Add 1
Row Add 2
Row Add 3
DIN N
DIN M
15h
70h
Status
80h
Col Col Row Row Row Add 1 Add 2 Add 1 Add 2 Add 3
DIN N
DIN M
15h PROGRAM
70h
Status
70h
Status
Serial Input
PROGRAM
Last Page - 1
Last Page
Poll status until: I/O6 = 1, Ready To verify successful completion of the last 2 pages: I/O5 = 1, Ready I/O0 = 0, Last page PROGRAM successful I/O1 = 0, Last page - 1 PROGRAM successful
Don't Care
57
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved.
2Gb, 4GB, 8Gb: x8, x16 NAND Flash Memory Timing Diagrams
2Gb, 4GB, 8Gb: x8, x16 NAND Flash Memory Timing Diagrams
Figure 56:
CLE
BLOCK ERASE Operation
CE#
tWC
WE#
tWB tWHR
ALE
RE#
tBERS
I/Ox
60h
Row Add 1
Row Add 2
Row Add 3
D0h ERASE Command
Busy
70h READ STATUS Command
Status
Row Address
R/B#
AUTO BLOCK ERASE SETUP Command
I/O0 = 0, Pass I/O0 = 1, Fail
Don't Care
Notes: 1. See Table 10 on page 27 for actual values.
Figure 57:
CLE
RESET Operation
www..net
CE# tWB WE# tRST R/B#
I/Ox
FF RESET Command
PDF: 09005aef814b01a2 / Source: 09005aef814b01c7 2_4_8gb_nand_m49a__2.fm - Rev. A 3/06 EN
58
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved.
2Gb, 4GB, 8Gb: x8, x16 NAND Flash Memory Package Dimensions
Package Dimensions
Figure 58: TSOP Type I
20.00 0.25 18.40 0.08 0.50 TYP PLASTIC PACKAGE MATERIAL: NOVOLAC EPOXY PLATED LEAD FINISH: 90% Sn, 10% Pb OR 100%Sn 0.25 PACKAGE WIDTH AND LENGTH DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 PER SIDE.
PIN #1 INDEX
12.00 0.08
0.20 0.05
0.25
0.10 0.15 +0.03 -0.02 SEE DETAIL A 1.20 MAX +0.10 -0.05
GAGE PLANE 0.10
0.50 0.1
DETAIL A
0.80
Note:
All dimensions in millimeters.
www..net
(R)
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 prodmktg@micron.com www.micron.com Customer Comment Line: 800-932-4992 Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners.
PDF: 09005aef814b01a2 / Source: 09005aef814b01c7 2_4_8gb_nand_m49a__2.fm - Rev. A 3/06 EN
59
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved.
2Gb, 4GB, 8Gb: x8, x16 NAND Flash Memory Revision History Revision History
Rev. A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3/06 * Initial release.
www..net
PDF: 09005aef814b01a2 / Source: 09005aef814b01c7 2_4_8gb_nand_m49a__2.fm - Rev. A 3/06 EN
60
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved.

▲Up To Search▲

Price & Availability of MT29F2G08AACWP

	To Download MT29F2G08AACWP Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .